This invention relates to a substrate bias generator for producing a potential in a semiconductor substrate, and more particularly to such a generator used with a dynamic memory cell in the form of an integrated circuit including, as the fundamental element, at least one MOS field effect transistor which is abgreviated hereinafter to an "MOSFET".
Conventional substrate bias generators have comprised the MOS capacitor and one pair of serially connected MOSFET's with the gate electrode connected to the drain electrode disposed on one of opposite main faces of the P.sup.- type semiconductor substrate and interconnected so that the MOS capacitor is connected to the junction of the MOSFET's and one of the MOSFET's includes a source electrode normally put at a ground potential while the other MOSFET has the drain electrode connected to an electrode on the other main face of the substrate. Therefore a parastic diode is formed between a pair of N.sup.+ type semiconductor regions forming an electrode for the MOS capacitor and a combined drain and source region of both MOSFET's respectively and the substrate. While those regions and the substrate are attended with parastic capacitances to ground.
With a voltage in the form of a square pulse applied to the MOS capacitor to put the substrate bias generator in operation, electrons due to an electric charge on the parastic capacitor attendant on the substrate are injected into the substrate through the parastic diodes, on the one hand, and through the other MOSFET and the other main face of the substrate, on the other hand. That portion of the electrons passed through the parastic diodes are soon recombined with holes forming majority carries within the substrate to disappear while that portion thereof passed through the MOSFET are instantaneously recombined with holes on a portion of the other main face of the substrate contacting the electrode thereon. Therefore the shortage of holes is developed in the substrate resulting in the generation of a negative potential in the substrate. This substrate potential is developed on the electrode on the other main face of the substrate.
Conventional substrate bias generators such as described above have been difficult to be used with the dynamic memory cell in the form of an integrated circuit disposed on the same semiconductor chip as the generator. It is assumed that the dynamic memory cell includes a single MOSFET and a single MOS capacitor serially connected to each other and stores data expressed by a binary ONE by having the MOS capacitor charged to a high potential. Under these assumed condition, some of the electrons passed through the parastic diodes in a mating substrate potential device might be caught by the MOS capacitor in the cell. As a result, the MOS capacitor changes from the high potential to a low potential which may reach a ground potential corresponding to a binary ZERO as the case may be. This has resulted in malfunction of the dynamic memory cell that a binary ZERO is read out although the binary ONE ought to have been written in the cell.
Accordingly, it is an object of the present invention to provide a new and improved substrate bias generator for producing a potential in a semiconductor substrate disposed in an integrated circuit on a semiconductor chip to permit a very small number of electrons to be injected into an associated semiconductor substrate to cause the principal factor for malfunctioning a dynamic memory cell in the form of an integrated circuit disposed on the same chip as the generator.